Realization of sigma-delta DAC for audio application on FPGA
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Today, data converters are extensively used in embedded systems for a large number of applications. Data converters can have a big impact on power consumption on small embedded systems. Thus, designing data converters with lower power consumption and high performance is an important subject. In this thesis, a proposed solution for a complete Sigma-Delta (S-D) digital to analog converter (DAC) for audio application is presented. The DAC is implemented on a field programmable gate array (FPGA), and the audio performance of the implementation is tested. A single sided pulse width modulation (PWM) DAC is implemented in register transfer level (RTL) code, and used as a comparison to the S-D DAC implementation. Both the S-D and PWM DAC is synthesized in TSMC's 55-nm technology, and a power estimation on the netlists is performed. The S-D DAC implementations worked as expected, and successfully played music on an audio system. The performance of the S-D DAC implementation is limited by poor switching characteristics of the digital pad on the FPGA and Intersymbol interference (ISI). A total harmonic distortion (THD) of -82.2dB was measured at 3kHz using 16 bit samples. This is equivalent to an effective number of bits (ENOB) of 13.4 bits. The harmonic distortion varied depending on the input frequency, and increased for the lower frequencies. At 100Hz, a THD of -56.3dB was measured, equivalent to an ENOB of 9.1 bits. In scenarios where the single sided PWM scheme and the designed S-D DAC are both applicable, the PWM DAC used up to 40 times less power. Suggestions for reducing the S-D DAC's power consumption are presented, which could reduce this power gap. The S-D DAC has a clearly better audio performance than the single sided PWM DAC. In scenarios where both are applicable, the choice is between a good audio performance or a low power consumption.