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Design of Low-Power Front-End Integrated Circuits for In-Probe Ultrasound Applications

Joozdani, Hourieh Atarzadeh
Doctoral thesis
Åpne
Fulltext not avialable (Låst)
Permanent lenke
http://hdl.handle.net/11250/2447480
Utgivelsesdato
2017
Metadata
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  • Institutt for elektroniske systemer [1548]
Sammendrag
This thesis explores the design and implementation of low-power integrated

circuits for in-probe ultrasound applications. In such systems, the power requirement

is very tight to prevent over-heating of the tissue. In this work,

we consider CMOS integration with capacitive micro-machined ultrasonic

transducers (CMUT), which have small dimensions, and therefore, the overall

area for the electronics is very limited. This research aims to develop

and implement circuits for realization of such miniature low-power in-probe

ultrasound systems.

The first part of the thesis explores the design and implementation of a

low-power, low-noise variable gain transimpedance ampli_er (TIA). The TIA

amplifier as the first amplifier in the receiver chain is designed to provide

variable gain, while adding the minimum possible noise to the transducer

noise. A prototype of the chip is fabricated using a 65nm CMOS process

technology. A transimpedance gain range of 79_97dB is measured. A noise

figure (NF) of 3dB at a 5MHz center frequency, with only 180_W power

consumption is obtained, and a total chip area of 76_m_50_m is achieved.

Afterward, the design of one receive channel as a partial implementation

of a digital beamforming system (DBF) is discussed. For this purpose, one

variable gain amplifier, and an ADC as the main building blocks for one

receive channel are implemented. The main key challenge in DBF systems

is the requirement for the ADC power consumption, since a dedicated ADC

is required for each single channel. In this work, a very low-power successive

approximation register (SAR) ADC is employed to limit the power consumption

of each receive channel. In addition, by using the ADC gain adjustments

along with TIA variable-gain ampli_cation, the overall dynamic range is improved.

The circuit is reconfigured for two operation modes, high-dynamicrange

mode, and low-power mode. The chip is designed and fabricated in

a 65nm standard CMOS process technology. An overall dynamic range of

72 dB is measured from the receiver circuit. The overall power consumption

of the receiver is limited to only 240_W for a sampling frequency of

30 MHz, and it occupies an area of 76_m_170_m. Based on the low power

consumption and the small chip area obtained, the receiver circuit design

can be scaled up in the future to a fully-integrated receiver circuit capable

of reading out a 2D array with hundreds of ultrasound elements.

In the last part of the thesis, we investigate a 3D-IC integration with

CMUT transducer. By stacking dies vertically, the available area for electronics

circuits can be more efficiently used. A stochastic flash ADC is implemented

in a 3D stacked IC. An all digital scalable system is obtained

by using only the digital standard cells and standard digital tools. Some

additional in-house tools were used to implement through silicon via (TSV)

insertion for 3D-IC implementation. In this work, the ADC is partitioned

into two stacked dies, mainly by considering separating the analog and the

digital parts. Two di_erent integration topologies for 3D-IC and the CMUT

array are considered and compared. A comparison of two different TSV insertion

methods is performed in the 3D stacked TSV implementation. The

3D-IC is implemented using 130nm Globalfoundries device technology and

TSV technology. A comparison of the performance between the 2D and 3DIC

implementation is performed to demonstrate the 3D bene_ts. A 20%

improvement in power consumption is obtained in the 3D implementation,

owing to the smaller interconnect parasitics. Thanks to the vertical stacking

dies, a 40% footprint reduction is achieved in the 3D implementation.
Utgiver
NTNU
Serie
Doctoral theses at NTNU;2017:155

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