|dc.description.abstract||The electrophoretic display (EPD) technology has great potential for use in small sized, low power portable devices and Internet of Things (IoT) applications. Due to its capability of true bistability and reflectivity, it can show static images in ambient light without the need of any flowing current. The required power for image updates is found to be highly dependent on the image pattern and driving circuitry architecture. If the driving circuitry is designed specifically for low power consumption and occasional image update, small size EPDs can potentially be integrated in products that never before had the opportunity of an integrated display.
Based on a theoretical and practical analysis of the EPD and its driving circuitry, trade-offs and power-reduction techniques are highlighted in this thesis. The the- oretical analysis is approached by dividing the driving circuitry into smaller sub- circuits or common building blocks. Each block is thereafter broken down and analyzed individually. A conceptual low power EPD module is then presented at higher abstraction levels. The practical experiments and analysis is based on a commercially available small size EPD. Different image updating techniques and driving pulse lengths are tested to find the optimal optical performance with min- imum energy consumption.
High driving voltages in the range of ±15V and updating times of several sec- onds is typically used for operation of EPDs. This is to achieve best possible optical performance and user experience. The high voltage sub-circuits is found to typically constitute for 90% of the total power consumption. By trading off fast response time and best optical performance with lower driving voltages, the total energy consumption is estimated to be reduced by more than one order of magnitude. Techniques such as unipolar driving waveforms and image updates in several stages at faster stage times can be used in combination. Theoretically, the driving voltages can be reduced to ±2.5V with a total updating time in less than one second. This leads to a typical reduction of 20-40% in optical perfor- mance. By designing a single chip EPD module based on lower driving voltages, it is estimated that the driving circuitry can potentially have an average power consumption below 1mW. This is less than 5% of the total worst case power con- sumption compared to the commercially available hardware tested in this thesis.||