| dc.description.abstract | The buffered clock tree structure is commonly used to distribute the clock signal to the memory elements in digital circuits. Since the clock signal is used as a temporal reference, it has to be distributed to the registers with decent timing characteristics and low skew. In order to achieve this, buffers and inverters are inserted in the clock tree, typically by a synthesis tool.
The clock tree is a major contributor to the power consumption. This is a result of a combination of high switching activity, due to the high frequency of the clock signal, and high total load in the buffers, registers and other cells. In order to reduce the power, clock gates are inserted in the clock tree, disabling the clock signal for unused logic. In this project, clock skew, buffer area and power consumption are considered the most important clock tree parameters.
The clock-tree synthesis functionality of the Synopsys® IC Compiler tool has been explored. The goal of this exploration is to illustrate trade-offs and examine how the different options affect the synthesis results. Synthesis results on a generated test design and a real Bluetooth Smart design show cost reduction when the skew target is increased from the default zero skew target. By increasing the skew target to 0.5 ns for the generated design, the buffer area is reduced by 2 168 µm2 (58%), while the dynamic and static power are reduced by 0.41 mW (10%) and 0.94 nW (21%), respectively. The reductions are less significant in the Bluetooth Smart design, however, comparable in absolute values. By increasing the skew target to 1.0 ns, the buffer area is reduced by 1 284 µm2 (21%), while the dynamic and static power consumption are reduced by 0.19 mW (3.3%) and 0.7 nW (0.5%), respectively. The increased clock skew of the Bluetooth Smart design does not show any significant increase in hold time violations cost.
A multi-level module-level clock gating strategy has been implemented in the Bluetooth Smart design. In this strategy, an additional layer of clock gates has been inserted between the existing module-level and the clock source. Results indicate a dynamic power reduction of about 0.04 mW (18%) in a selected low-power scenario, without any significant cost increase, compared to the unmodified structure. However, the control circuit for the new level has not been implemented. Further work is therefore needed to determine if the tested strategy is beneficial. | |
