Design of Nanoscale CMOS Integrated Circuits for Ultrasound In-Probe Electronics
MetadataShow full item record
This thesis presents five kinds of architectures of the low-noise single-ended to differential variable gain amplifier (VGA) for 2-6 MHz second harmonic cardiac ultrasound imaging systems. The presented VGAs, as the first stage of the front-end in the receiver, exhibit the low-noise performance while adjusting the output amplitude of the received echo signals in a large dynamic range (DR) by tuning the gain. This makes the VGAs to be feasible to replace the low-noise amplifier (LNA) and the time-gain compensation (TGC) block in a traditional medical ultrasound imaging system, and results in a more simplified architecture with lower power consumption. The VGAs are designed for three-dimensional (3D)/4D medical ultrasound imaging probes, in which thousands of transducer elements and receive channels will be integrated into a single probe. The power consumption for each receive channel should be as low as possible to make the patients feel comfortable during the real process. It therefore raises a challenge for the VGA to operate at a low noise level while maintain low power consumption. Because the transducer in ultrasound imaging systems is a single-ended device, to suppress the second harmonic distortion (HD2) of the VGA, the single-ended to differential conversion is employed in all VGAs presented in the thesis. VGA 1 is a two-stage charge sampling switched-capacitor VGA (SC-VGA); and consists of a charge sampling amplifier (CSA) with a fixed integration time as the first stage to achieve the low noise and high sensitivity, and a SC-VGA as the second stage with a 8-bit binary-weighted capacitor array to vary the gain from -14 dB to 14 dB while complete the single-ended to differential conversion. VGA 1 has the simulated input referred noise (IRN) of 6.56 ƤA √Hz at 4 MHz and 25.3 nArms at a sampling frequency (fs) of 30MHz, and the HD2 of -62 dB at 150 mVpp output. The simulated power consumption is 1.25 mA at a supply voltage of 1.8 V in 0.18 μm CMOS technology, which matches well with the measured power consumption. The active size is 310 μm × 370 μm in 0.18 μm CMOS technology. VGA 2 is a fully two-stage SC-VGA and established upon two same operational trans-conductance amplifiers (OTA). Total 10-bit binary-weighted capacitor arrays divided in two stages tune the gain from -14 dB to 32 dB. The first stage has the gain tuning range from 0 dB to 18 dB, and the second stage tunes the gain from -14 dB to 14 dB while complete the single-ended to differential conversion. The measured HD2 is less than -50 dB, and the measured integrated output noise in 2-6 MHz band is -64 dBm at the maximum gain and a 30 MHz sampling frequency. The power consumption is 900 μA at a supply voltage of 1.6 V in 0.18 μm CMOS technology. The active size is 387 μm × 502 μm. VGA3 is an inverter-based two-stage SC-VGA. The first stage is an inverter-based SC-VGA with a 6-bit binary-weighted capacitor array, and the second stage is a differential amplifier with a 4-bit thermometer-coded resistor array as the load. The total gain range is from -9 dB to 21 dB, the measured HD2 is less than -50 dB, the 2-6 MHz output integrated noise is -72 dBm at the maximum gain and a sampling frequency of 30 MHz, and the power consumption is 150 μW at a 1 V supply voltage. The active size is 109 μm × 164 μm in 0.18 μm CMOS technology. VGA 4 is a fully inverter-based two-stage SC-VGA with total 12-bit binary-weighted capacitor arrays. Since the single-ended to differential conversion is based on SC circuit in VGA 4, different from VGA 3, the HD2 performance is improved. The measured HD2 is better than -50 dB, 2-6 MHz integrated noise at the output is -75 dBm at the maximum gain and a sampling frequency of 30 MHz, and the power consumption is the same as VGA 3, 150 μW at a 1 V supply voltage. The active size is 245 μm × 134 μm in 0.18 μm CMOS technology. VGA 5 is an inverter-based continuous-time VGA (CT-VGA) in 65 nm CMOS technology, which consists of three equal inverters and resistive feedback arrays to tune the gain from -1 dB to 21 dB for a 2D piezoelectric transducer (PZT) model as the signal source. The measured HD2 is better than -55 dB, and the integrated noise in 2-6 MHz band at the output is -67 dBm at the maximum gain. The power consumption is 54 μW at a 0.5 V supply voltage. The active size is 154 μm × 102 μm. VGA 1 to VGA 4 were fabricated in the same chip of 0.18 μm CMOS technology. The 30MHz of the sampling frequency is used for VGA 1 to VGA 4 considering the resolution of the beamforming in the receiver. Because of the fabrication error in the tape-out, the control bit of the output buffer for VGA 1 is damaged (which is also the last bit of the shift register in the chip to connect to the output pad), and except the power consumption other performances of VGA 1 cannot be measured. VGA 5 was fabricated in 65 nm CMOS technology. Comparing the proposed VGAs, the power consumption is reduced gradually from VGA 1 to VGA 5, while the performances are improved, which makes VGA 4 and VGA 5 as good candidates for the application of 3D/4D second harmonic cardiac ultrasound imaging probes.