Minimizing Latency in Stream-Based Compression with the use of FPGA Dynamic Partial Reconfiguration: Hardware Parallelism Analysis
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Dynamic partial reconfiguration is a relatively new technique that permits the reconfiguration of portions of an FPGA without stopping all on-chip logic. The confluence of the additional adaptability of dynamic partial reconfiguration, and the massive parallelism FPGAs are capable of, lend themselves to new applications. This paper will begin to explore the possibilities of applying partial reconfiguration, as realized in the Altera series V FPGAs, to a compression algorithm. The selected compression algorithm is known as LZW, or Lempel-Ziv-Welch compression, and is an adaptive lossless algorithm that builds a dictionary of common sequences as compression progresses, and emits short codes for common sequences.An implementation of the algorithm benefits from the distributed memory and highly parallel nature of an FPGA, as the dynamic dictionary is subject to a full search for every new input sequence, and is updated with every emitted code word.In considering the benefits of implementing functionality with dynamic partial reconfiguration, a metric indicating the possible benefit must be selected. With regards to LZW, as it is an inherently variable compression rate algorithm, a more appropriate metric than coding rate is coding latency, or the average time necessary to compress or decompress a given block of data. Thus, an optimized implementation of LZW on a partial reconfiguration capable FPGA would most likely seek to either reduce time per encoded sequence, or maximize sequences that may be detected simultaneously.This report addresses the implementation of LZW on a partial reconfiguration capable Altera Cyclone V FPGA, with and without using the reconfiguration capabilities, and evaluates functional and physical requirements for the effective usage of runtime reconfiguration.