UVM Verification Framework

Abstract

The importance of verification is increasing with the size of hardware designs,and reducing the effort required for is necessary to increase productivity. Thisthesis covers the creation of a reusable verification framework for processorverification using the Universal Verification Methodology (UVM). The frameworkis used to verify three simple processor designs to evaluate its potential for reuse.The three processors include a synchronous, asynchronous and a stack basedprocessor. A pure UVM implementation is evaluated against the use of externalchecking by Assertion Based Verification (ABV), which is found to provide abetter overview. The framework is shown to be highly reusable, especially forinput generation, and can be used for both synchronous and asynchronousdesign. The high reusability is a key part of increasing productivity gained byremoval of redundant work. This framework is intended as a proof of concept,and is does not provide a complete verification for each of the designs.