| dc.description.abstract | The goal of this thesis was to find an alternative to a reference video scaler, providing the same or higher visual quality at faster operation, requiring less FPGA area and memory.The first part of the report is used to lay a theoretical foundation within the field of video and image scalers. It is shown how the problem of video scaling is equivalent to the problem of discrete signal resampling in signal theory, and therefore also bound by the sampling theorem. The report explains why the the sinc function is the ideal interpolation kernel for signal reconstruction, and how the windowed sinc function is utilized in video/image scaling applications. Three different video scaler algorithms Winscale, Edgeprocessor and Polyphasic FIR-filter Lanczos2 has been purposed. All algorithms are explained in theory and system architectures are suggested. Through visual quality tests based on matlab models, were the conclusion drawn that Winscale provides varying, non-predictable lower visual quality compared to the reference scaler and is not a suitable alternative. The adaptive Edgeprocessor shows potential as lower complexity alternatives providing better visual quality through the use of basic edge-detection and more complex calculations than Winscale. FIR-filter Lanczos2 is still seen as the better choice of implementation, as both Winscale and Edgeprocessor depends on a prescaler when downscaling below scale factor 0.5. Configurable IP-core scalers from Altera has also been suggested, providing equal visual quality at maximum frequency requiring less FPGA resources. This solution would not provide full customizability and debug properties, as the source-code is not provided. The IP-cores can be configured with the most common interpolation kernels (Nearest, Bilinear, Bicubic, Polyphase).The use of dynamic reconfigurable FPGAs in video scaling applications are shortly discussed, as the research provided only a limited amount of literature and examples within this specific field. My own thoughts and ideas on how reconfigurability may be utilized are presented. Allthough no actual implementation of the described algorithms and system architectures is done, the thesis lays a theoretical foundation for future implementation of the three purposed scaler architectures. | nb_NO |
