Path Delay Fault Test and BIST

Abstract

The advanced semiconductor manufacturing processes, integrated chip design methodology and high level integrated circuit (IC) packaging are constantly giving challenges to the test industry and demands an efficient circuit test techniques. Even though, several existing techniques and algorithms have been used to test circuits, still test industries are in need to develop new techniques which can test logic, memory and analog circuits of the chip. Indeed, it is beneficial to find modified and improved algorithms to test the on-chip circuitries which can significantly reduce the test time, and to achieve fair fault coverage. This work considered test techniques which are based on Built-In-Self-Test (BIST) method and path delay fault (PDF) testing.

However, the testing strategy depends on the type of the circuit (combinational circuits, sequential circuits, memory circuits). Therefore, in first part of this research, we focused on path delay fault testing of combinational circuits as well as content addressable memory (CAM). We introduced an enhanced path delay fault simulator for combinational circuits using modified path selection and simulation algorithms with 20% speed-up factor. We also proposed a test method to detect critical path delay faults in CAM systems using a newly proposed low power ternary CAM (TCAM) cell structure with low time complexity complement bit walk (CBW) algorithms.

In the second part, we also addressed the issue of adapting BIST techniques in combinational circuits (ex: Arithmetic BIST), and memory circuits (ex: Static RAM BIST, and CAM BIST). The proposed approach contributes in building an efficient and flexible CAM system with an emphasis on its maximum critical search speed measurement under worst case operation. The experimental results show that the presented BIST methodology is effective and provides improved search delay measurement such as 1.72ns. In addition, our SIC based test generator with Arithmetic BIST (ABIST) is quite useful for detecting the K-longest path-delay faults of the microprocessor. We also presented a programmable built-in self-test (PBIST) methodology for embedded SRAMs. This BIST logic adapts the test controller with micro code encoding technique in order to control test operation sequences. The experimental results show that this PBIST gives 17-47% improved area overhead and 16-41% enhanced speed.