| dc.description.abstract | A growing trend among DAC designs and electronics production in general is performing signal processing digitally, rather than analog. Modern DAC designs often include digital preprocessors intended to simplify the analog part of the design. DAC's are often implemented using a zero-order hold, which introduces a sinc roll-off distortion in the frequency domain. At $f = 0.8F_{\rm s}/2$ ($80\%$ of Nyquist) the zero order hold attenuates the baseband spectrum by 2.4 dB, which is a considerable loss for most wideband applications. Digital interpolation reduces the attenuation caused by the zero-order hold and lessen the demands for the analog design by allowing a greater transition width for the analog reconstruction filter. Another feature of the preprocessor is digital frequency translation. When using this feature one can avoid band-limited noise after analog upconversion and liberates the user to pick off the shelf analog filters. This thesis presents digital preprocessing as a generic term for interpolation, frequency translation and inverse sinc filtering. A 8x digital interpolator is shown to reduce the sinc roll-off attenuation caused by the zero-order hold from 2.4 dB to 0.04 dB and reduces the requirements set on the analog reconstruction filter by lowering the required filter order from $N = 11$ to $N = 5$. Linear phase half-band filters turn out to be very efficient for this application, since they can potentially reduce the required filter order in each interpolation stage by 4, when implemented in hardware. Omitting interpolation means an inverse sinc filter needs to be included to counter the zero-order hold roll-off. We then show that the filter order of the inverse sinc filter increase in an approximately linear fashion as the passband ripple is lowered. Experimental work showed that very small passband ripples resulted in large filter orders for the inverse sinc filter. The preprocessor presented in this paper allows for multiplexing, which in turn control the functionality of the frequency shifter. 2-, 4-, and 8-element frequency shifters are shown to provide adequate functionality without amounting to a great implementational cost. In addition we will see that digital frequency shifting enables image rejection after analog upconversion, thus simplifying the analog design beyond the interpolator. When we reach the implementational discussion of the preprocessor, we will see how the system can be modeled in Simulink and then how generated HDL-code is analyzed in PlanAhead. Interpolation using a transposed direct form filter structure is then compared to a polyphase filter structure, where we evaluate usage of key components such as multipliers, LUTs and registers. The trade-offs involved with using a digital preprocessor prior to a DAC is the need for extra digital logic, and with that the need for extra processing power and a greater tolerance for system group delay. However, this inconvenince is often worth risking as it greatly reduces the complexity of the analog design. | nb_NO |
