Software Defined Radio for High-speed Pico Satellite Downlink

Abstract

The subject of this thesis is to study the potential of implementing an FPGA based software defined radio as a high speed downlink for a Cubesat student satellite.This report starts with a theoretical analysis of the link budget elements to determine a probable best case downlink speed. The link budget shows that creating a software defined radio that dynamically operates at the limit, can in best cases reach data rates up to 5-10 Mb/s. Next the report looks at the possibility of implementation of the SDR on the Altera DE2 development board. This is evaluated in context of the DE2 board being used as a development platform and basis for a later software radio module on board a Cubesat student satellite. This includes techniques, ideas and generic building blocks for use in later SDR projects and what optimizations are needed in order to allow room for further development. Although a fully working SDR design is not presented, the modules that require the most resources has been studied. The focus of the discussion is to assess the possibility of an SDR implementation on a Cubesat, and if its development can be done using the Altera DE2 development board. Based on compilation results of resource demanding blocks, it is concluded that when using optimizations there are more than enough resources on the Altera DE2 board to implement an SDR design. A working SDR should be possible to implement using less than a tenth of the FPGA resources.