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Self Reconfiguration of Clock Networks on FPGA: Methodology for partial reconfiguration of synchronous modules at run-time
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In this thesis, methodology for partial self-reconfiguration of synchronous modules has been developed. A simple software-based scheduler has been built for scheduling synchronous modules on the FPGA. The motivation behind this was that partial reconfiguration of synchronous modules at run-time had not been performed earlier in the AHEAD-project. Also, the project report written by the same author as this thesis has shown that a synchronous module can be replaced in a bitfile. However, the project report did not perform this reconfiguration at run-time.Based on the project report, the problem has been decomposed and simple tests using clocked flip-flop designs have been performed on the FPGA. These tests forms a proof-of-concept for partial self-reconfiguration of synchronous modules on the Virtex-4 FPGA. However, the tests also showed that the reconfiguration time was quite high. It took several seconds to write one partial bitstream to the configuration memory.Vegard Endresen has previously made a backend module for data transfer between the HWOS and a reconfigurable module. Experiments were performed in this thesis to see if the clocking methodology could be integrated into this backend module. The module could be built with the methodology, but a running solution on the FPGA was not shown.The software part of the HWOS was rewritten from scratch as the previous version was not thoroughly analyzed. A round-robin scheduler using priority queues has been implemented. A test-driven development technique has been used for development, hopefully making the system more robust. The scheduler is a part of a daemon running on the embedded system, where a message server handles requests for new processes and a placer places new tasks on the FPGA. The complete system was initially based on ideas and code developed by Sverre Hamre and Vegard Endresen in previous AHEAD-projects.