dc.contributor.advisor | Larsen, Bjørn B. | nb_NO |
dc.contributor.author | Tyridal, Torbjørn | nb_NO |
dc.date.accessioned | 2014-12-19T13:46:25Z | |
dc.date.accessioned | 2015-12-22T11:44:57Z | |
dc.date.available | 2014-12-19T13:46:25Z | |
dc.date.available | 2015-12-22T11:44:57Z | |
dc.date.created | 2011-06-14 | nb_NO |
dc.date.issued | 2006 | nb_NO |
dc.identifier | 422930 | nb_NO |
dc.identifier.uri | http://hdl.handle.net/11250/2370174 | |
dc.description.abstract | This report presents the master thesis on migrating embedded systems from 8 to 32 bit CPU.It accounts for the study of different CPU architectures, their properties and use, with an emphasize on differences presented to the programmer. It gives a summary of market segments for the two bit widths and points out benefits of using a 32 bit CPU.In the second part obstacles when migrating software and hardware from existing designs and general design considerations, like Electromagnetic compliance, required in a 32 bit world is discussed and analyzed.Finally it describes an effort to optimize Atmel s new, under development, on chip debugger (OCDX), by replacing the 8 bit AVR Mega128 with Atmel s latest 32 bit AVR32 AP7000. It was found that the OCDX s data throughputrequirements are too high to be handled efficiently with the AVR32, and the current FPGA implementation is suggested to continue. | nb_NO |
dc.language | eng | nb_NO |
dc.publisher | Institutt for elektronikk og telekommunikasjon | nb_NO |
dc.subject | ntnudaim:1225 | no_NO |
dc.title | Migration from 8 to 32 bit microcontroller | nb_NO |
dc.type | Master thesis | nb_NO |
dc.source.pagenumber | 55 | nb_NO |
dc.contributor.department | Norges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjon | nb_NO |