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dc.contributor.advisorLarsen, Bjørn B.nb_NO
dc.contributor.advisorHaugen, Bjørn
dc.contributor.authorØybø, Espen Drivenesnb_NO
dc.date.accessioned2014-12-19T13:46:04Z
dc.date.accessioned2015-12-22T11:44:36Z
dc.date.available2014-12-19T13:46:04Z
dc.date.available2015-12-22T11:44:36Z
dc.date.created2010-11-10nb_NO
dc.date.issued2010nb_NO
dc.identifier369187nb_NO
dc.identifierntnudaim:5422
dc.identifier.urihttp://hdl.handle.net/11250/2370091
dc.description.abstractMarket demands forces designers and engineers to develop more advanced products quicker and at lower prices. Computer simulations is one way of increasing development speed, thereby lowering the time spent verifying and testing the product. The most common way to do numerical analysis (computer simulations) on a variety of problems (exmaples include, but are not limited to strengt, thermodynimcal and/or fluid problems) is the Finite element method. The most computationally intensive part of the finite element analysis is the solving of the linear equation Ax = b. One of the most effective ways to solve this equation is by using a decomposing algorithm called LDLT decomposition.In this thesis a hardware LDLT decomposer is studied. It is shown how the number of memory reads needed is able to be roughly halved if implemented parallelly, however the memory bandwidth still proves to be the bottleneck of this operation.nb_NO
dc.languageengnb_NO
dc.publisherInstitutt for elektronikk og telekommunikasjonnb_NO
dc.subjectntnudaim:5422no_NO
dc.subjectSIE6 elektronikk
dc.subjectDesign av digitale systemer
dc.titleHardware Based LDLT Decomposition For Large Matricesnb_NO
dc.typeMaster thesisnb_NO
dc.source.pagenumber59nb_NO
dc.contributor.departmentNorges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjonnb_NO


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