Built-in Self-Test (BIST) for SRAM in Deep Sub-Micron

Abstract

This thesis is a study of the fault mechanisms in static random access memories (SRAMs) and an implementation of a built-in self-test (BIST) module for these memories. Special emphasis has been put on the state-of-the-art functional fault models, as well as and march tests that cover the modeled faults in linear time. Furthermore, the topology of modern SRAMs has been studied, and the necessary countermeasures have been incorporated in the BIST scheme.The BIST module is implemented as a generator program that produces synthesizable RTL code in SystemVerilog. It is highly flexible and allows any combination of march tests to be included in the module through an easy-to-use configuration file. Moreover, a selection of topological data-backgrounds and addressing directions are available for inclusion, in order to exploit the extra fault coverage that these stresses can provide in deep sub-micron SRAMs.