Asynchronous design of CPU elements

Abstract

The clock in digital circuits often cause large portions of the power consumption. Designing circuits without clocks, asynchronous circuits, has been proposed as a method to save power. It is also important to study alternatives to clocked synchronization when the clock becomes a limiting factor to scalability.Designing circuits without clocks is not as widespread as traditional clocked circuit design, but different practical solutions have been proposed. In this thesis, asynchronous design is explored by implementing an asynchronous Advanced Encryption Standard module. The module is implemented using Petrify to synthesize Signal Transition Graphs for control, and standard synthesis tools is used for implementation of the datapath. It is found that the designed module have good performance with a low area overhead. The designed module also consumes no power while idle, while it is found that active power probably corresponds to a synchronous implementation, as the same amount of combinational switching (work) must be done, regardless of whether an asynchronous or synchronous control circuit is used. The results indicate that computational intensive applications probably does not benefit much from asynchronous control.