| dc.description.abstract | A problem with image sensors today, is that they contain defect pixels. By utilizing an image processing algorithm for defect pixel correction, image quality can be increased and costs per produced sensor can be reduced.This thesis had the goal of designing an embedded FPGA-based system for defect pixel correction. The FPGA in the designed system, is capable of receiving an image with defects, correcting it and sending the result back to a PC. A control function is partitioned in software and runs on a soft core CPU on the FPGA, while detection and correction of defect pixels are done in hardware. A detection algorithm which detects most point defects and some adjacent defects, while avoiding false positives, is designed. The implemented correction algorithm is an adjusted version on the alpha-trimmed mean filter. The algorithms are based on a single frame approach, using a 3x3 squared window of adjacent pixel values.By comparing corrected test images to the original, the quality of the correction was measured with mean absolute error and peak signal-to-noise ratio. Ten test image were selected to represent a diverse test base. The average PSNR ranged from 50.5 dB to 24.9 dB, for defect densities between 0.0001 and 0.1. Mean absolute error ranged from 0.04 to 1.98. The system is capable of correcting defects with a throughput of 270.000 pixels per second. The numerous read/write cycles from software to DDR2 memory and PIO ports, are the main bottlenecks. External inputs to the hardware datapath could increase the throughput significantly. | nb_NO |
