5.8GHz, 1W high efficiency Power Amplifier in 90nm CMOS
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PREFACE This master s thesis was written as the final step towards my master s degree, and it thereby marks the ending of my time at NTNU. The master s thesis was developed due to a proposal made by Texas Instruments, under the offered supervision of Oddgeir Fikstvedt. My supervisor at NTNU was Morten Olavsbråten. This report describes the design of a power amplifier in the 90nm CMOS technology. The power amplifier is designed to deliver 1W output power at 5.8GHz with a peak efficiency of 50%. Both the class-E and the inverse class-D amplifier are described and examined, but the final choice in amplifier design is the inverse class-D amplifier. Simulation results on a realistic inverse class-D amplifier model are presented as the final outcome. Trondheim, 2009-07-16 Nina Tofte Røislien ABSTRACT Recently CMOS has been introduced as a technology for RF-front end applications. This results in higher levels of integration, which saves fabrication cost and area. The power amplifier often contributes to the highest power consumption, and the efficiency becomes very important. This master s thesis handles the design of a CMOS power amplifier at 5.8GHz. The design goals were an output power of 30dBm, a Power Added Efficiency of 50% and a gain of 25dB. The main challenge in the CMOS-technology is the low breakdown voltage. This leads to a higher current and a lower load resistance compared to traditionally used RF-technologies. This makes it harder to design a high efficiency amplifier because of more power loss in the parasitic, and a more complex matching network. Two different amplifiers were investigated, both of the switching type; the class-E amplifier and the inverse class-D amplifier (current mode). The class-E amplifier has been studied by others for this kind of use, and has an advantage because of the load network that is synthesized to give non-overlapping voltage and current, even if the device switching time is appreciable fractions of the ac cycle. One can also utilize the high output capacitance of the CMOS-transistor as part of the load network. The inverse class-D amplifier has an advantage of being differential which provides a higher voltage swing across the load, and thereby a higher load resistance and a lower current compared to the class-E. In contrast with conventional voltage-mode class-D amplifiers, the inverse class-D features zero voltage switching which eliminates the output capacitance discharge loss. This output capacitance is also utilized as part of the resonance filter in the load network. No previous work of others that uses the inverse class-D amplifier in a similar configuration (RF, CMOS) was discovered. It was found that the inverse class-D amplifier was the best suited for this application. The load resistance of the class-E amplifier became too low compared to the parasitic losses to achieve the design goals. The ground inductance was also totally destructive for the class-E waveforms because of the single-ended topology. Since the inverse class-D amplifier instantly showed much more promising behavior, no time was used trying to solve this problem. The resulting inverse class-D amplifier design has a peak efficiency of 51%, an output power of 30.04dBm. The gain is 25dB for an output power of 28dBm, but sadly it decreases below the design goal to 20.06dB at the point where Pout=30dBm and PAE=50%. ACKNOWLEDGEMENT I would like to give great thanks to Oddgeir Fikstvedt and Morten Olavsbråten for invaluable support during this time, and for making this thesis possible. I would also like to give great thanks Trond Ytterdal for his help with Cadence, and to Tore Barlindhaug for help with some fatal last minute Cadence problems.