Multiple Power Domains

Abstract

When new transistor technology is used in a microcontroller design, the transistors become smaller. They cannot withstand the same voltages as older technology, because of their size. The automotive industry still uses 5V as a standard voltage, and the automotive industry is a major costumer for microcontroller companies. The microcontroller must therefore be able to use5V. This must be done without the need of external voltage regulator. To still be a supplier to the automotive industry, the AVR needs to be able to withstand voltages up to 5.5V. The main problem with the new transistor technology is the leakage currents. Traditionally, the CMOS devices have used power only when during switching of logical levels. This is no longer true, since the leakage currents have become so large. When using new transistor technology, the dynamic power usage will be reduced, but the total power usage will be increased, if nothing is done to prevent it. One solution to this is to make a multiple power domain microcontroller. The idea is that one power domain can withstand voltages up to 5.5V. The microcontroller then uses an internal voltage regulator to scale down the voltage to a suitable level. The low voltage area will then have a suitable voltage level, which reduces both the dynamic- and leakage power usage. The different voltage domains uses different clock sources, so communicating between them requires both level shifters to deal with the different voltage levels, and synchronization logic to prevent metastability. This assignment uses two voltage domains, VIO and VCORE. Since voltage regulators are quite inefficient, it is most efficient to use only two domains. The VCORE domain contains most of the digital logic of the microcontroller, such as the CPU, SRAM and timers. This domain uses a high-speed clock source, and a VCORE data bus to communicate between each other. To communicate with the VIO domain, the data bus is connected to the VIO data bus through an asynchronous communication scheme block. This is because the VIO domain uses a low speed clock source. The usage of individual clock sources prevents clock skew problems that may occur when passing level shifters, and there is power saving by using only a low speed clock source on the VIO domain. The VIO domain contains the Power Management Unit (PMU). The PMU shall control the power usage of the microcontroller. During active mode, the PMU can set unused modules in sleep mode, or shut them completely off. Most of the power savings are during sleep mode though. This is because a microcontroller such as the AVR spends most of the time in sleep mode. To reduce the power usage in sleep mode, the leakage currents needs to be reduced. The best way of doing so is to disconnect the power from the circuits. If the voltage regulator is disconnected, and all the inputs are set to high impedance, the VCORE domain is completely disconnected from the power, and uses absolutely no power. An asynchronous wake up circuit is designed to make it possible to wake up the microcontroller from a sleep mode without the usage of synchronized digital logic. Then the low frequency oscillator can be turned off, and even more power is saved. The major disadvantage of the multiple power domain solution is the start up time from a sleep mode. If the power to the low voltage area is disconnected, the start up requires that all the capacitors become charged before the chip can start running again. The oscillator is shut off, and it takes time to stabilize the oscillator. Especially since the oscillator requires some stability in the voltage, and the voltage may not stable until the capacitors are charged. Simulations shows that the multiple power domain solution has great potential of power saving. The proposed asynchronous wake up circuit uses only 1.2275nA. This is significantly smaller than the AVR uses in the deepest sleep mode today. To get a secure microcontroller, a reset circuit has to be on to be able to reset the AVR if necessary. The power usage of the reset circuit used today is confidential Atmel information, and cannot be published in this assignment. By looking at the data sheet of a pico power circuit of the AVR, the ATmega329p, one can see that in the deepest sleep mode, the microcontroller uses 40nA at 1.8V. By assuming that the reset circuit does not use more that half of this current, the total amount of power that saved during a sleep mode by using the multiple power domain solution is about 47%.