Design of a high IIP2 2.4GHz RF Front-end
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This master thesis presents the design of a high IIP2 direct-conversion receiver front-end, consisting of a LNA and I- and Q-channel mixers. The front-end is implemented in a 0.18 μm technology with 1.8V supply voltage. Problems that are especially severe for direct-conversion receivers are presented; 1/f-noise, DC offset, and second-order nonlinearity, with particular attention to the latter. Methods to improve the IIP2 are presented and explored in the design of the front-end. The complete front-end has -19.7 dBm IIP3, 4 dB noise figure, and consume 7.4mA of current from a 1.8V supply. Through mixer load tuning an IIP2 of more than +48 dBm is achieved for the front-end.