## Investigation of errors in open-loop sigma-delta modulators utilizing analog modulo integrators

##### Master thesis

##### Permanent lenke

http://hdl.handle.net/11250/2369283##### Utgivelsesdato

2006##### Metadata

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##### Sammendrag

This thesis is divided into two parts, the design of a practical first order open loop sigma-delta modu- lator using discrete components, and simulation of a third order OLSD ADC to investigate the consequences of circuit imperfections - and determining circuit requirements if the ADC should be used in a GSM system. The practical modulator is designed as a first order OLSD ADC, with standard discrete components such as operational amplifiers and switches, and a microcontroller with a built in ADC. The practical circuit uses surface mount capacitors with a tolerance of 20%, resulting in poor matching and inaccurate behavior of the modulo integrator. Despite the poor matching, the OLSD ADC shows a distinct noise shaping, with a slope of about 20dB per decade. The quantization noise is not the dominating noise source in the circuit, and the quantizer resolution must to be set to four bits or less to achieve any improvement in performance over the standard ADC. The third order modulator is modeled and simulated at a behavior level using VHDL-AMS. The ideal circuit confirms the results from the preliminary project [12], where the quantizer resolution had to be equal to or larger than the modulator order to obtain proper noise shaping. The simulations shows that the ideal third order modulator with a four bit quantizer can achieve a SNR of 88:51dB, and an ENOB of 13:78bits within a 200kHz band. The third order modulator is simulated with circuit imperfections to determine the effect of these when there is no feedback present. Introducing finite gain in the integrators results in harmonic distortion at the output. This harmonic distortion is a result of leakage of the internal reset signal in the integrators. By setting the gain in all three integrators to 2OSR = 42dB, the SNR of the third order modulator sinks to 71:74dB. The gain in the ¯rst integrator is increased to 60dB, and the SNR raises to 84:52dB. The first integrator is the most crucial to the performance of the modulator, as is the case for conventional sigma-delta ADCs. The circuit is also simulated with capacitance mismatch and comparator o®set in the modulo integrator. These two imperfections results in the same error - the output voltage from the integrator di®ers from the ideal case. Simulations show that the total voltage error should be significantly less than 0.5VLSB to obtain the noise shaping. If the integrator output error is too large, the noise shaping will totally disappear. In general, it has been proved that the OLSD modulator with modulo integrators works as intended, the quantization noise is shaped like in conventional sigma-delta modulators. The modulator is very sensitive to capacitor mismatch and parasitics. The e®ect of these capacitor imperfections will increase as the quantizer resolution increase, because the error will cover more units of VLSB. It is important to minimize these capacitor effects, as increased quantizer resolution will allow a greater input signal swing.