dc.contributor.advisor | Ytterdal, Trond | nb_NO |
dc.contributor.advisor | Marienborg, Jan-Tore | |
dc.contributor.author | Torgersen, Svend Bjarne | nb_NO |
dc.date.accessioned | 2014-12-19T13:43:46Z | |
dc.date.accessioned | 2015-12-22T11:41:26Z | |
dc.date.available | 2014-12-19T13:43:46Z | |
dc.date.available | 2015-12-22T11:41:26Z | |
dc.date.created | 2010-09-03 | nb_NO |
dc.date.issued | 2009 | nb_NO |
dc.identifier | 347856 | nb_NO |
dc.identifier | ntnudaim:4792 | |
dc.identifier.uri | http://hdl.handle.net/11250/2369209 | |
dc.description.abstract | A comparator-based switched capacitor integrator for use in a Delta Sigma ADC has been designed. Basic theory about comparator-based circuits has been presented and design equations have been developed. The integrator had a targeted performance of a bandwidth of 1.5MHz with a SNR of 80dB. Due to the lack of a complete modulator feedback system, the integrator was simulated in open-loop. For the integrator not to saturate in open-loop, an overshoot calibration circuit was enabled during the simulation. This resulted in a severe deterioration of the integrated signal. The results are therefore significantly lower than expected, with a SNR of about 39dB but can be expected to be better in a closed-loop simulation. The power consumption of the implemented modules is 0.43mW. However, this is without several modules which were implemented as ideal. | nb_NO |
dc.language | eng | nb_NO |
dc.publisher | Institutt for elektronikk og telekommunikasjon | nb_NO |
dc.subject | ntnudaim | no_NO |
dc.subject | SIE6 elektronikk | |
dc.subject | Krets- og systemdesign | |
dc.title | Comparator-Based Switched-Capacitor Integrator for use in Delta-Sigma Modulator | nb_NO |
dc.type | Master thesis | nb_NO |
dc.source.pagenumber | 54 | nb_NO |
dc.contributor.department | Norges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjon | nb_NO |