DVB-S2 FEC Encoder: Implementation of DVB-S2 FEC encoder in FPGA
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This Master Thesis describe how DVB-S2 Forward Error Correction (FEC) encoding can be implemented in hardware like a FPGA. It include the design, simulation, verification and synthesis of a complete encoder for the DVB-S2 FEC system. First the Thesis gives a introduction to the history behind DVB-S2 and the FEC system. It describe shortly the theory behind the error correcting codes used in the FEC, BCH and LDPC codes. To get an effective implementation in hardware it was necessary to studies different papers and articles for efficient encoding of BCH and LDPC codes. Since the SystemC simulator for DVB-S2 FEC Encoder that was developed in a earlier project assignment contained errors it was necessary to fix that but also include some expansion. It was necessary to do a more detailed verification of the simulator as well. The main contribution in this Thesis is the design, simulation and verification of a DVB-S2 FEC Encoder described in VHDL code. It gives a description for each of the three modules (BCH, LDPC and Interleaver) that is included and the result from the simulation and verification. The final step in this Thesis was to synthesis the encoder and confirm that it should be possible to be implemented in a FPGA. The DVB-S2 FEC encoder has been designed using VHDL code in a way that the author thinks is the most effective way from the available papers and articles. The encoder is verified by simulation in Modelsim where the result is compared with a reference created in the SystemC simulator. During the simulation of the encoder several frames (up to 100 frames per rate) where encoded and compared with a reference and no dissimilarities where found. Almost all modules in the encoder is not platform specific except one sub module in LDPC Encoder (Lookup Table). That lead to that only one FPGA vendor is used during simulation/verification and synthesis. The chosen vendor is Xilinx since that was the type FPGA the author is most familiar with. When compare the synthesis result for this encoder against other available encoders on the marked the areal (slices) this encoder uses is half of what the other encoders use but when comparing RAM usage this encoder is not so effective as the others. The maximal clock frequency for the encoder implemented into a Virtex4 FPGA from Xilinx is achieve when using ISE as a synthesis tool. The result was 227MHz with the speedgrade set to -12 (the best speedgrade) and when using a Virtex5 FPGA the maximal clock frequency was even higher (290MHz). Since the encoder is capable to encode one bit per clock cycle the bitrate become the same as maximal clock frequency. It must be mention that the maximal clock frequency is only a estimate after synthesis, for accurate timing information Place and Route must be performed. The one thing that not have been done according to the problem description is testing on FPGA hardware. Due to limited time and shortage of FPGA evaluation kits this was not possible to be executed. As a final conclusion the author means that the implementation was successful although it was not physical tested in a FPGA. The speed requirement is fulfilled and the required slice areal is half of what other encoders use but the RAM Block usage is higher.