CMOS Class D Audio Amplifier Implementations for Microcontroller Circuits
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A class D amplifier implementation on an AVR 8-bits microcontroller is presented in this thesis. The solution uses a pulse modulation scheme known as uniform sampled pulse width modulation (UPWM). Eight times interpolation and noise shaping are used to reduce the PWM resolution from 2.89 GHz to 90.8 MHz. A noise shaper provides a minimal reduction of the signal quality within the audioband. A pre-compensation method called WPWM is added to reduce the harmonics occurring when UPWM is used. To be able to implement the amplifier on the AVR, a multiply accumulate (MAC) module and an address generator module were added to the microcontroller core and the memory access had to be increased from 8 bits to 16 bits. The extra modules required can be realized by approximately 2500 NAND2 equivalents. The minimum clock speed the system can run on is 39.2 MHz. The implemented amplifiers audio quality results: Parameter Condition Result Frequency response 20 Hz 20 kHz 0.14 dB THD 20 Hz 20 kHz 60 dB SNR 20 Hz 20 kHz 87.9 dB IMD CCIF two tone 58 dB The results are sufficient for most types of handheld devices. The main contributions done in this thesis are: 1.Extracting a good solution that can be implemented on the AVR with reasonable changes. 2.Optimizing the solution for the AVR, and map extra resources needed. 3.Optimizing the calculation cost needed in the filters that does interpolation. 4.Designing an address generator to reduce the time used to access memory. 5.Implementing and verifying the solution on the AVR.