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dc.contributor.advisorLarsen, Bjørn B.nb_NO
dc.contributor.authorRustad, Andersnb_NO
dc.date.accessioned2014-12-19T13:42:54Z
dc.date.accessioned2015-12-22T11:40:13Z
dc.date.available2014-12-19T13:42:54Z
dc.date.available2015-12-22T11:40:13Z
dc.date.created2010-09-02nb_NO
dc.date.issued2007nb_NO
dc.identifier346700nb_NO
dc.identifier.urihttp://hdl.handle.net/11250/2368908
dc.description.abstractWhen Digital Signal Processors were first introduced in the early 80 s they were significantly faster than general microprocessors at performing digital signal processing (DSP) algorithms. The advantages of having specialised DSP processors are getting smaller and smaller, especially for low-end applications. Atmel is currently developing a new series of microcontrollers based around the new ultra low cost AVR10 8/16-bit CPU. This CPU does not natively support DSP operations. The objective of the thesis has been to develop an ultra low cost DSP extension for the new AVR10 CPU. The DSP extension should have a multiply-accumulate operation and it had to be able to generate memory addresses for coefficients and data. The extension was implemented with a four/five-cycle multiply-accumulate operation to keep the cost down. The AVR10 CPU can operate in parallel with the extension to function as an address generator and read new input data from the memory. The extension supports different modes of operation such as, saturation arithmetic and scaling. It also supports both integers and fractional numbers in the Q1.15 and Q1.31 format. The performance of the extension is limited by the data memory and the speed new input data can be read from the memory. In the current implementation of the AVR10 CPU it only has 8-bit access to the data memory. The CPU use eight clock cycles to read two 16-bit operands from the memory (four cycles to read and four cycles to increment/decrement pointers). The effect the bus width has on the memory area was examined to find the cost of increasing the bus width. The results showed that for larger memory blocks it is better with 16-bit bus width (with 8-bit and 16-bit access) than 8-bit bus width. Another solution is to connect several smaller memory blocks together to get a memory with 16-bit bus width. The synthesis results for the extension showed that the area of the AVR10 CPU and the DSP extension was just under 4900 NAND gate equivalents (the constraint set by Atmel). Several benchmarks were developed and the AVR10 CPU with the extension was compared to some of the first DSP processors from Texas Instruments. It had about the same performance as the TMS32010 and with an increase in area (600 NAND gate equivalents) the performance could be doubled. Newer DSP processors have a much higher performance with higher frequency and several processing units operating in parallel, but for a much higher cost.nb_NO
dc.languageengnb_NO
dc.publisherInstitutt for elektronikk og telekommunikasjonnb_NO
dc.subjectntnudaimno_NO
dc.titleDSP Extension for AVR10 CPUnb_NO
dc.typeMaster thesisnb_NO
dc.source.pagenumber126nb_NO
dc.contributor.departmentNorges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjonnb_NO


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