Blar i Institutt for elektroniske systemer på emneord "ntnudaim:5790"
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Modeling and Design of a Dual-Residue Pipelined ADC in 130nm CMOS
(Master thesis, 2012)A 9-bit 50M S/s dual-residue pipelined ADC is modeled and analyzed. Thefirst stage is a modified pipelined ADC stage, while the other stages uses aninterpolator to resolve the signals, the focus is on designing these stages. ...