Blar i Institutt for datateknologi og informatikk på tidsskrift "IEEE Symposium on High-Performance Computer Architecture (HPCA)"

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    • Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors 

      Alipour, Mehdi; Kumar, Rakesh; Kaxiras, Stefanos; Black-Schaffer, David (Peer reviewed; Journal article, 2020)
      Flexible instruction scheduling is essential for performance in out-of-order processors. This is typically achieved by using CAM-based Instruction Queues (IQs) that provide complete flexibility in choosing ready instructions ...

    • Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures 

      Zhao, Xia; Eeckhout, Lieven; Jahre, Magnus (Peer reviewed; Journal article, 2022)
      Heterogeneous architectures with latency-sensitive CPU cores and bandwidth-intensive accelerators are attractive as they deliver high performance at favorable cost. These architectures typically have significantly more ...

    • Freeway: Maximizing MLP for Slice-Out-of-Order Execution 

      Kumar, Rakesh; Alipour, Mehdi; Black-Schaffer, David (Journal article; Peer reviewed, 2019)
      Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level cache access latencies. While out-of-order (OoO) cores, and techniques building on them, are effective at exploiting MLP, they deliver ...

    • Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services 

      Nishtala, Rajiv; Petrucci, Vinicius; Carpenter, Paul; Själander, Magnus (Peer reviewed; Journal article, 2020)
      Many of the important services running on data centres are latency-critical, time-varying, and demand strict user satisfaction. Stringent tail-latency targets for colocated services and increasing system complexity make ...