Predictable computing for cyber-physical systems
Abstract
Cyber-physical systems encompass a vast category of systems where computers operate in feedback with physical systems. Cyber-physical systems hold the potential for enormous societal impact, comparable to that of the internet revolution in the 2000s. However, unlike typical internet applications, where crashes and downtime are commonplace and acceptable, cyber-physical systems depend on correctness and predictability. Cyber-physical systems often interact with critical infrastructure or humans and failures are unacceptable. The correctness of a cyber-physical system depends on a predictable interaction between the computers and the physical system. There are two important aspects of this interaction. The first aspect is the value of the signals being communicated between the computer and the physical system, e.g. the setpoint of an actuator. The second aspect is the time at which this signal is being communicated. Most cyber-physical systems today are built with technology that admits non-determinism concerning both the values of the signals and the timing of the signals.
To realize the full potential of cyber-physical systems, engineers need access to high-performance computers that are easy to program to deliver reliable, predictable and correct computations. Three research areas will be important to achieve this vision. First, a better understanding of cyber-physical systems requirements for predictability is needed. Particularly in the field of multi-sensor fusion where jitter in the timestamping of sensor measurements can be thought of as noise coloring the measurement. Second, new architectures, languages and models for general-purpose CPUs that emphasize both performance and predictability are needed. Particularly, there is a need for predictable multi-core systems and distributed systems. Lastly, new models and languages are needed to efficiently design correct computations on emerging heterogeneous computer architectures such as System-on-Chip (SoC) Field Programmable Gate Arrays (FPGA).
This thesis is a compilation of peer-reviewed articles addressing topics within these three research areas. On the topic of understanding the predictability requirements of a cyber-physical system, one paper is included. It introduces the Syncline model, an intuitive performance model relating timestamping accuracy, sensor noise and the dynamics of the system.
On the topic of predictable general-purpose CPU, three papers are presented. The first paper provides support for Lingua Franca, an emerging design language for cyber-physical systems, on resource-constrained microcontrollers. The second paper introduces InterPRET a new time-predictable multicore processor architecture The third paper extends Timed C, a C-based programming language with timing semantics, with primitives for inter-task communication over networks, enabling simplified design of distributed systems.
On the topic of predictable heterogeneous architectures, this thesis include three papers. The first paper presents fpga-tidbits, a framework for designing and evaluating accelerators for SoC FPGAs. The second paper builds on this framework to implement an accelerator for the linear programming problem known as the assignment problem. The third and last paper introduces hardware reactors, a model of computation for hardware-software codesign and an extension to Lingua Franca enabling single-source reactor-oriented hardware-software codesign.
Has parts
Paper A: Jellum, Erling Rennemo; Bryne, Torleiv Håland; Johansen, Tor Arne; Orlandic, Milica. The Syncline Model - Analyzing the Impact of Time Synchronization in Sensor Fusion. I: Proceedings 6th IEEE Conference on Control Technology and Applications. (CCTA) IEEE conference proceedings 2022 s. 1446-1453 https://doi.org/10.1109/CCTA49430.2022.9966179 - © IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Paper B: Jellum, Erling Rennemo; Lin, Shaokai; Donovan, Peter; Soyer, Efsane; Shakir, Fuzail; Bryne, Torleiv Håland; Orlandic, Milica; Lohstroh, Marten; Lee, Edward A.. Beyond the Threaded Programming Model on Real-Time Operating Systems. NG-RES workshop https://doi.org/10.4230/OASIcs.NG-RES.2023.3 CC-BY Creative Commons Attribution 4.0 International license
Paper C: Austad, Henrik; Jellum, Erling Rennemo; Hendseth, Sverre; Mathisen, Geir; Bryne, Torleiv Håland; Gregertsen, Kristoffer Nyborg; Albrektsen, Sigurd Mørkved; Helvik, Bjarne Emil. Composable distributed real-time systems with deterministic network channels. Journal of systems architecture 2023 ;Volum 137. https://doi.org/10.1016/j.sysarc.2023.102853 This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).
Paper D: Jellum, Erling Rennemo; Lin, Shaokai; Donovan, Peter; Jerad,Chadlia; Wang, Edward; Lohstroh, Martin; Lee, Edward A.; Schoeberl, Martin. InterPRET: A Time-predictable Multicore Processor. CPS-IoT Week '23: Proceedings of Cyber-Physical Systems and Internet of Things Week 2023 Pages 331 - 336 This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1145/3576914
Paper E: Jellum, Erling Rennemo; Umuroglu, Yaman; Orlandic, Milica; Schoeberl, Martin. FPGA-tidbits: Rapid Prototyping of FPGA Accelerators in Chisel. 26th Euromicro Conference on Digital System Design 2023, DSD https://doi.org/10.1109/DSD60849.2023.00031 © IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Paper F: Jellum, Erling Rennemo; Orlandic, Milica; Brekke, Edmund Førland; Johansen, Tor Arne; Bryne, Torleiv Håland. Solving Sparse Assignment Problems on FPGAs. ACM Transactions on Architecture and Code Optimization (TACO) 2022 ;Volum 19.(4) Article No.: 55, Pages 1 - 2 https://doi.org/10.1145/3546072 This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).
Paper G: Jellum, Erling Rennemo; Schoeberl, Martin; Lee, Edward A.; Orlandic, Milica Codesign of Reactor-oriented Hardware and Software for Cyber-Physical Systems. - This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record is published in ACM Transactions on Reconfigurable Technology and Systems (TRETS), https://doi.org/10.1145/3672083