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dc.contributor.authorSalvesen, Peter
dc.contributor.authorJahre, Magnus
dc.date.accessioned2023-01-23T13:05:22Z
dc.date.available2023-01-23T13:05:22Z
dc.date.created2022-09-28T13:40:01Z
dc.date.issued2022
dc.identifier.citationIEEE computer architecture letters. 2022, 21 (2), 97-100.en_US
dc.identifier.issn1556-6056
dc.identifier.urihttps://hdl.handle.net/11250/3045367
dc.description.abstractMulti-core processors suffer from inter-application interference which makes the performance of an application depend on the behavior of the applications it happens to be co-scheduled with. This results in performance variability, which is undesirable, and researchers have hence proposed numerous schemes for predicting the performance slowdown caused by inter-application interference. While a slowdown predictor's primary objective is to achieve high accuracy, it must typically also respect resource constraints. It is hence beneficial to be able to scale the resource consumption of the predictor, but state-of-the-art slowdown predictors are not resource-scalable. We hence propose to construct predictors using Linear Model Trees (LMTs) which we show to be accurate and resource-scalable. More specifically, our 40-leaf-node LMT-40 predictor yields a 6.6% prediction error compared the 8.4% error of state-of-the-art GDP at similar storage overhead. In contrast, our LMT-10 predictor reduces storage overhead by 34.6% compared to GDP while only increasing prediction error to 9.4%.en_US
dc.language.isoengen_US
dc.publisherIEEEen_US
dc.titleLMT: Accurate and Resource-Scalable Slowdown Predictionen_US
dc.title.alternativeLMT: Accurate and Resource-Scalable Slowdown Predictionen_US
dc.typePeer revieweden_US
dc.typeJournal articleen_US
dc.description.versionacceptedVersionen_US
dc.rights.holder© IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en_US
dc.subject.nsiVDP::Datateknologi: 551en_US
dc.subject.nsiVDP::Computer technology: 551en_US
dc.source.pagenumber97-100en_US
dc.source.volume21en_US
dc.source.journalIEEE computer architecture lettersen_US
dc.source.issue2en_US
dc.identifier.doi10.1109/LCA.2022.3203483
dc.identifier.cristin2056396
dc.relation.projectNorges forskningsråd: 286596en_US
cristin.ispublishedtrue
cristin.fulltextpostprint
cristin.qualitycode1


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