| dc.description.abstract | Today, the emerging technology of LVDC and MVDC grids is under extensive research. These grids ease the integration of distributed electricity generation systems and offer several advantages over the AC counterparts, such as lower transmission losses at the same voltage level. However, the lack of a high-performance protection scheme against DC short-circuits is currently the main showstopper for their further development. Three main circuit breaker topologies have been proposed for the fault clearance in DC grids. Among them, the solid-state breaker exhibits the highest speed of breaking operations at a cost of high conduction losses caused in power semiconductor devices. This PhD thesis investigates primarily the design of solid-state DC breakers with the aim of minimizing their conduction losses. For this purpose, the conducting performance of several commercial Silicon and SiC semiconductor technologies with blocking voltage in the range of 1200-1700V have been extensively evaluated. Experimental results revealed that the normally-ON SiC JFETs achieved the lowest conduction losses for mediumpower LVDC and MVDC solid-state breakers. On the other hand, at high-power MVDC applications, three high-voltage power semiconductor devices are identified. It has been shown that the IGCT-based breakers exhibit the lowest conduction losses. However, to avoid complicated gate driver designs utilized in IGCTs, the use of the gate voltage-controlled IGBTs for high-power solid-state breakers is imposed.
Additionally, this PhD thesis proposes the concept of applying the maximum gate voltage (overdrive) to the active power semiconductor devices used in solid-state breakers in order to minimize the conduction power losses. Especially in SiC MOSFETs and in normally-ON SiC JFETs, the forward voltage drop is reduced significantly compared to IGBT-based semiconductor technologies. In particular, experimental results showed that the normally-ON SiC JFET achieves a conduction loss reduction up to 33% at 55% of normalized current when overdriving.
Three overvoltage suppression configurations used in solid-state breakers for 700-1800VDC applications have been experimentally evaluated in terms of electrothermal performance and passive components requirements. The feasibility and the application-oriented usability of MOVs as an overvoltage suppression configuration for medium-power solid-state LVDC and MVDC breakers has been demonstrated. In addition, the applicability of using both RCD snubber circuits and MOVs as an overvoltage suppression configuration for high-power MVDC solid-state breakers is also revealed.
The voltage level of an MVDC grid can be significantly higher than the blocking voltage of a high-voltage semiconductor device. This imposes the need for series-connecting a high number of devices for the breaker design. However, this practice introduces design challenges, such as uneven voltage distribution among the devices during the breaking operation. A hybrid method for designing a solidstate MVDC breaker employing series-connected IGBTs with minimum snubber capacitances requirements is proposed. This method is based on the combination of RCD snubber circuits and a gate coupled transformer. The proposed method minimizes the snubber capacitances by 60% compared to a reference configuration which only consists of RCD snubber circuits, when a gate signal propagation delay of 1 s between two series-connected IGBTs is introduced. Finally, in a 3kVDC study, experimental results showed that by keeping the same snubber capacitance, the voltage difference between two IGBTs was measured to be 380V without the use of the gate coupled transformer. On the other hand, in the proposed scheme, the corresponding voltage difference was reduced to 60V .
Finally, the design of an automatic and self-powered solid-state breaker using normally-ON SiC JFETs suitable for a 700VDC grid is proposed. This breaker exhibits low conduction losses and it also eliminates the need for external auxiliary circuits used for fault sensing and gate-driver supply. The effectiveness of the breaker has been experimentally validated by interrupting a fault current of 33A within 330 s. | |
