Understanding the Nonlinear Behaviour and Synchronizing Stability of a Grid-Tied VSC Under Grid Voltage Sags
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Transients of a typical grid synchronizing VSC are closely associated with the over-current and over-voltage in circuits. Previous analysis in evaluating such transient phenomenon usually ignore the nonlinear control effects of the VSCs (e.g. phase-locked-loop, PLL). Although this assumption allows a simpler analysis of the transient process, it may overlook potential stability issues on which the nonlinear controls may a great impact and the consequence of which is easily confused with the passive circuit transients. Therefore, this work aims to achieve a good understanding of the nonlinear control dynamics of the VSC and their impacts on the stability provoked by the grid voltage sags. To better reveal the mechanisms, the power control loop (PCL) and the PLLdominant dynamics are analysed separately with corresponding reduced-order nonlinear models. From which the grid synchronizing stability of the VSC is revealed, and a quantitative study of stability margin is presented through the calculation and evaluation of the critical clearing time (CCT). Based on this, CCT under various PLL bandwidths are evaluated, the results of which could facilitate the parameter design of PLL from a stability viewpoint. All the analyses are verified by time-domain simulations in PSCAD/EMTDC.