Tunnel FET Analog Benchmarking and Circuit Design
Journal article, Peer reviewed
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OriginalversjonIEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC). 2018, 4 (1), . 10.1109/JXCDC.2018.2817541
A platform for benchmarking tunnel field-effect transistors (TFETs) for analog applications is presented and used to compare selected TFETs to FinFET technology at the 14-nm node. This benchmarking is enabled by the development of a universal TFET SPICE model and a parameter extraction procedure based on data from physics-based device simulators. Analog figures of merit are computed versus current density to compare TFETs with CMOS for low-power analog applications to reveal promising directions for the system development. To illustrate the design space enabled by TFETs featuring sub-60-mV/decade subthreshold swing, two example circuits including a picopower common-source amplifier and an ultralow-voltage ring oscillator are demonstrated.