An insight into geometry and orientation of capacitors for high-speed power circuits
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SiC transistors can switch extremely fast. Often turn-off di/dt is reduced to limit the turn-off over voltages due to the stray inductances in the commutation loops. Thus, the potential low switching losses are not met. One of the benefits of designs with SiC devices is the possibility of low switching losses and therefore high switching frequencies. This opens for the paradigm shift in power electronics. For utilizing the fast switching potential, a low inductive circuit layout of the commutation loop consisting of the transistor, diode, connections and the DC-link capacitor is indispensable. Low inductive transistor case and busbars are analysed by the authors before. Employing low stray inductance DC-link capacitors is a must for realizing the low stray inductance designs. The methods used to connect the DC-link capacitors to the system, such as the busbar, is equally important. The paper analyses the geometry and orientation of the DC clamping capacitor for minimizing the SiC transistor turn-off over voltages. In addition, by reviewing the commercially available low inductance DC-link capacitors with different physical size and terminations, this paper presents the design of a DC-link for a 100 kW full-bridge AC-DC-AC converter. Two approaches; first, measuring the parasitics of the components themselves, such as capacitor and transistor module by impedance analyser; and second, computing the parasitics of the bussing structure and connections via FEA tool; are adopted throughout this work. Based on this, the breakdown of the total switching loop stray inductance contributed by each parts is illustrated, from which the major conclusions are drawn.