Implementation and testing of shadow tags in the M5 simulator

Abstract

The performance gap between CPU and main memory is a limiting factor for the performance in computers. Caches are used to bridge this gap. Caches give higher performance if the correct blocks are in place when the CPU needs them. Prefetching is a technique that tries to fetch the correct blocks into cache before the CPU references them. Prefetching can be implemented in software and hardware. Software prefetching is static and cannot be adjusted in runtime. Hardware prefetching can be adjusted dynamically in runtime. Shadow tag based prefetching is a scheme for dynamically adjusting the configuration of a hardware prefetcher. The configuration is based on statistics retrieved from cache performance counters. Shadow tag based prefetching was tested on a uniprocessor architecture in my fifth year specialization project, on the SimpleScalar simulator. This gave an increase in performance on the SPEC CPU2000 benchmark suite. Uniprocessors represent the past in computer architecture. Chip-multiprocessors (CMP) are the new standard as they provide higher throughput with lower design complexity and power consumption. There is therefore a need for a shadow tag implementation on a CMP simulator. Shadow tags are regular cache address tags that are kept in a shadow cache. The shadow tags do not have the corresponding data arrays. Different prefetching configurations are tested on the shadow tags to see how they perform compared to the prefetching configuration used in the L2 cache prefetcher. The best configuration is applied to the L2 cache prefetcher dynamically. M5 is a complex and flexible simulator platform based on object-orientation. Software objects simulate the behavior of hardware units. I extend M5 with shadow tags in this project. This involves extending the Bus and Cache implementation in M5. The shadow tag extension is intended to be used also by other students and researchers. The extension has been validated on an uniprocessor and a CMP architecture.