COMPARING BINARY, CSD AND CSD4 APPROACHES ON THE ASPECT OF POWER CONSUMPTION IN FIR FILTERS USING MULTIPLIERLESS ARCHITECTURES ON FPGAS

Abstract

The aim of this thesis is to compare several different algorithms of FIR-filter design on the aspect of the amount of power they consume. Three different approaches are presented: One based on binary, two's complement representation of the coefficients in the filter. The second approach is based on CSD representation, and the third approach is based on CSD4 representation of the coefficients. The three approaches are compared due to their overall power consumption when implemented on an FPGA. In theory, representing coefficients in CSD number representation, yields a reduction of non-zero bits in the implementation by 33% compared to binary representation for long wordlengths. Representing them in CSD4 yields a further reduction of 36% over CSD representation. These are the theoretical numbers. This thesis presents a practical example, simulated in distributed arithmetic on Xilinx's FPGAs. 12 different filters have been simulated with number of taps between 4 and 200. An automatic design generation tool has been developed in C to ease the process of VHDL-code generation. The automation tool generates two basic architectures, each consisting of three designs. The designs are one design based on binary numbers, one design based on CSD and the last design based on CSD4 number representation. The simulations have been done on Xilinx - Project Navigator 7.1.02i, on device family Spartan II for the smaller filters and on Spartan 3 for the larger filters. The power analysis is done using Xilinx - XPower. The results from this thesis are not what the theory states: For filters with number of taps between 4 and 32, simulated on Spartan II, the results show an increased difference between the binary approach and the CSD4 approach power consumption, in favour of the binary one. On average for these designs, binary consumes 24,5% less power than CSD4. The filters with larger number of taps (62-200) simulated on Spartan 3, the results show a power consumption equal for all the three different approaches in a filter. In other words, the percentage difference between binary, CSD and CSD4 numbers are almost zero. In this thesis it has not been shown that the binary approach in any case consumes less power than the CSD4 approach. This is, however, only a novel start on the big research field exploiting the possibilities of CSD4 number representation. The future will show whether the CSD4 number representation will turn out to be beneficial or not and if the use of it in FIR-filters will exceed the efficiency of RAG-n and other currently optimal algorithms.