Spam Filtering With Approximate Search in FPGA Hardware

Abstract

Spam poses a complex threat to organizations, business and end users. Large high speed networks require fast spam filtering applications to be able to do search through the large amount of emails that are received. The processing speed of traditional software processors are not increasing as much as the increasing amount of data that are to be processed. When spammers also try to bypass a spam filter by obfuscating the spam keywords, the workload of the processors increases even more.

By outsourcing specific tasks of anti-spam solutions, faster processing times can be achieved. This thesis implements the approximate search algorithm onto a Field Programmable Gate Array, FPGA, board, in order to find obfuscated spam keywords faster than the traditional software implementation. The algorithm has the ability to work in a bit parallel fashion, and hence utilize the parallel feature of hardware.

This thesis compares a traditional software implementation of the anti-spam measure approximate search to a hardware implementation of the algorithm. The results shows that a hardware implementation of this algorithm can give record braking processing times. To perform these tests, a hardware program was developed in Verilog Hardware Language, HDL. The program takes a pattern input and searches for approximate matches in a search text. The algorithm used is the bit parallel approximate search using Levenshtein distance.