Noise tolerant voltage-controlled LC oscillator circuits for deep submicron VLSI system-on-a-chip radio circuits
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This thesis studies the problems with maintaining the spectral purity of fully integrated VCO circuits for radio frequency synthesizers in single-chip system designs. LC tank circuit oscillator circuits are shown to convert amplitude variation in the tank circuit voltage into frequency modulation, if voltage dependent capacitances are present in the tank circuit. Since the parasitic capacitances of the gain transistors and the capacitance of the varactor device in a VCO circuit are voltage dependent, any interfering signal, that is able to modulate the amplitude of the VCO tank circuit voltage waveform, is converted to FM sidebands in the output signal spectrum. It is also shown that the AM-FM conversion may be prohibited under some conditons. A new method for simulating the steady-state voltage waveform of an LC tank circuit oscillator is presented. In this method, one complete oscillation cycle is simulated piecewise, employing the known solution of the damped harmonic motion equation. The voltage-dependent parameters of the equation are updated in the beginning of each segment. The steady state is found by matching the initial conditions and the final conditions of one complete oscillation cycle, using a numerical optimization algorithm. The method avoids finding the solution of the differential equation with variable coefficients. For minimizing the sensitivity of integrated VCO circuits to the intra-chip noise sources, this work proposes minimizing the AM-FM conversion by designing the VCO in the way that the voltage dependent capacitances of the oscillator core circuit are made to cancel each other’s effects on the oscillation frequency at some amplitude level. Experimental results demonstrate 15 dB suppression of the sidebands due to the modulated tail current noise in a negative-Gm spiral inductor PFET VCO circuit. The varactorless prototype circuit is implemented in a 0.35 µm CMOS technology. The measured tuning range of the 3 GHz back gate tuned VCO circuit is 10 %, and the current consumption of the core circuit is 2.5 mA. The phase noise level is -110 dBc at 500 kHz offset frequency. The last part of this thesis discussses the problems with modeling and characterizing small MOS transistors, and presents characterization of 28 µm wide MOSFSET devices. A new method for extracting the drain and source electrode resistances from the measured Z22 response is presented. The response is measured at a constant and very low signal frequency, with Vds = 0 V and with various gate-source bias voltage values. At low signal frequencies, the equivalent diagram of the MOSFET is dramatically simplified, since all parasitic capacitors of the device may be ignored. Consequently, the number of degrees of freedom in the curve fitting is reduced to only two.