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Static Instruction Scheduling for High Performance on Limited Hardware

Tran, Kim-anh; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Spiliopoulos, Vasileios; Kaxiras, Stefanos; Jimborean, Alexandra
Journal article, Peer reviewed
Accepted version
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Åpne
preprint.pdf (1.495Mb)
Permanent lenke
http://hdl.handle.net/11250/2464896
Utgivelsesdato
2017
Metadata
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  • Institutt for datateknologi og informatikk [3779]
  • Publikasjoner fra CRIStin - NTNU [19793]
Originalversjon
10.1109/TC.2017.2769641
Sammendrag
Complex out-of-order (OoO) processors have been designed to overcome the restrictions of outstanding long-latency misses at the cost of increased energy consumption. Simple, limited OoO processors are a compromise in terms of energy consumption and performance, as they have fewer hardware resources to tolerate the penalties of long-latency loads. In worst case, these loads may stall the processor entirely. We present Clairvoyance, a compiler based technique that generates code able to hide memory latency and better utilize simple OoO processors. By clustering loads found across basic block boundaries, Clairvoyance overlaps the outstanding latencies to increases memory-level parallelism. We show that these simple OoO processors, equipped with the appropriate compiler support, can effectively hide long-latency loads and achieve performance improvements for memory-bound applications. To this end, Clairvoyance tackles (i) statically unknown dependencies, (ii) insufficient independent instructions, and (iii) register pressure. Clairvoyance achieves a geomean execution time improvement of 14% for memory-bound applications, on top of standard O3 optimizations, while maintaining compute-bound applications' high-performance.
Utgiver
Institute of Electrical and Electronics Engineers (IEEE)
Tidsskrift
I.E.E.E. transactions on computers (Print)

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