Power Cycle Testing of Press-Pack IGBT Chips

Abstract

In this thesis the power cycling capability of individual press-pack IGBT chips is investigated. Press-pack is a packaging technology used for power semiconductors. For press-packs, both thermal and electrical contact to the semiconductor chip is obtained by the application of force on the package. Press-pack IGBTs is claimed by the manufacturers to be especially suitable for high-power applications with large variations in power output. Power cycle testing is an accelerated lifetime stress test, ideal for assessing the lifetime of components in such applications. In power cycle testing, a component is thermally cycled by on-state-losses from a current repeatedly turned on and off.

SINTEF Energy Research have in cooperation with Technical University of Chemnitz developed a 2000 A power cycle tester. Power cycling of press-pack IGBT discs in this tester revealed an unexpectedly short power cycling lifetime. To obtain a sufficiently high current rating, press-pack IGBT discs consist of many paralleled IGBT chips. SINTEFs hypothesis is that changes in the internal pressure distribution, caused by deformation of the press-pack housing during power cycling, have caused a destructive stress level for IGBT chips in certain positions inside the press-pack.

To investigate this hypothesis, test equipment for power cycling individual IGBT chips removed from press-pack discs have been developed in this master thesis. Two IGBT chips have been continuously power cycled for a considerable number of cycles under tough conditions. The results supports the hypothesis that the early failure of press-pack discs is caused by excessive stress on chips in certain locations. Since the lifetime of the individual chips was found to be 10 - 50 times longer than that of press-pack discs tested under similar stress, this conclusion is justified.