| dc.description.abstract | Model predictive control has been a topic of research for approximately three decades, and is considered one of the most important advances in process control. In this project, a model to simulate predictive control applied to a two level inverter has been developed. The first step was to develop a Simulink model for testing of predictive current control. Sampling periods of 25 µs and 1 µs for the predictive control algorithm was tested, to investigate the effect the frequency of predictions has on the performance. The conclusion was that a higher sampling frequency results in a significantly better performance.
For experimental purposes, the predictive control algorithm will be executed on a FPGA. Xilinx System Generator (XSG) was used to adapt this part of the Simulink model to consist of blocks from the XSG, and the predictive control algorithm was altered to be suitable for execution on a FPGA. Switching frequency reduction was added to the predictive control. Simulation with only current control resulted in a switching frequency of 43.8 kHz, which is not feasible for use in a physical circuit. The weight assigned to the current reference tracking versus the weight of the switching frequency reduction, can be specified by the use of a weighing factor, A. Simulations with different values of A were performed, and this showed that the switching frequency can easily be reduced by increasing A, but the cost is a less accurate current reference tracking.
The control method was tested in an experimental setup with a 20 kW IGBT inverter and a resistive inductive load. For this purpose the model was implemented in the RT-Lab environment, and custom RT-XSG communication blocks were inserted in the model to handle data transferring between the CPU, FPGA and inverter. The testing of the predictive control model on the experimental setup was not successful. There was no response from the system, and no switching occurred. It is believed that this is a result of an error in the data transfer from the CPU to the FPGA model. Troubleshooting to locate the error will be included in further work. | |
