A Cellular Automata Accellerator for SHMAC

Abstract

Energy usage is an increasingly limiting factor for modern micro processors. One of these limitations is that it is no longer possible to power up all the transistors of the processor at the same time. The Single-ISA Heterogeneous MAny-core Computer (SHMAC) project considers how a heterogeneous multi core architecture can be used to reduce these limitations. A heterogeneous multi core architecture can consist of a selection of different cores, where each of these cores can be better suited for a specific task. Some of these cores can be, or contain, accelerators; hardware designed to perform very specific tasks efficiently.

This thesis covers the implementation of a Cellular Automata (CA) accelerator, which can be configured to evolve time steps for 1D or 2D CA. A functional implementation integrated into SHMAC is presented and demonstrated by a few example applications, including pseudorandom number generation in a 1D CA, and Conway's Game of Life in a 2D CA. The resulting system merges an unconventional accelerator with a conventional processor.