dc.contributor.author | Zhang, Shiqing | |
dc.contributor.author | Naderan-Tahan, Mahmood | |
dc.contributor.author | Jahre, Magnus | |
dc.contributor.author | Eeckhout, Lieven | |
dc.date.accessioned | 2023-11-17T15:45:10Z | |
dc.date.available | 2023-11-17T15:45:10Z | |
dc.date.created | 2023-11-12T15:10:24Z | |
dc.date.issued | 2023 | |
dc.identifier.issn | 1556-6056 | |
dc.identifier.uri | https://hdl.handle.net/11250/3103330 | |
dc.description.abstract | MCM-GPUs scale performance by integrating multiple chiplets within the same package. How to partition the aggregate compute resources across chiplets poses a fundamental trade-off in performance versus cost and sustainability. We propose the Performance Per Wafer (PPW) metric to explore this trade-off and we find that while performance is maximized with few large chiplets, and while cost and environmental footprint is minimized with many small chiplets, the optimum balance is achieved with a moderate number of medium-sized chiplets. The optimum number of chiplets depends on the workload and increases with increased inter-chiplet bandwidth. | en_US |
dc.language.iso | eng | en_US |
dc.publisher | IEEE | en_US |
dc.rights | Navngivelse 4.0 Internasjonal | * |
dc.rights.uri | http://creativecommons.org/licenses/by/4.0/deed.no | * |
dc.title | Balancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUs | en_US |
dc.title.alternative | Balancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUs | en_US |
dc.type | Peer reviewed | en_US |
dc.type | Journal article | en_US |
dc.description.version | acceptedVersion | en_US |
dc.source.journal | IEEE computer architecture letters | en_US |
dc.identifier.doi | 10.1109/LCA.2023.3313203 | |
dc.identifier.cristin | 2195404 | |
dc.description.localcode | © Copyright 2023 IEEE - All rights reserved. | en_US |
cristin.ispublished | true | |
cristin.fulltext | postprint | |
cristin.qualitycode | 1 | |