Vis enkel innførsel

dc.contributor.authorZhang, Shiqing
dc.contributor.authorNaderan-Tahan, Mahmood
dc.contributor.authorJahre, Magnus
dc.contributor.authorEeckhout, Lieven
dc.date.accessioned2023-11-17T15:45:10Z
dc.date.available2023-11-17T15:45:10Z
dc.date.created2023-11-12T15:10:24Z
dc.date.issued2023
dc.identifier.issn1556-6056
dc.identifier.urihttps://hdl.handle.net/11250/3103330
dc.description.abstractMCM-GPUs scale performance by integrating multiple chiplets within the same package. How to partition the aggregate compute resources across chiplets poses a fundamental trade-off in performance versus cost and sustainability. We propose the Performance Per Wafer (PPW) metric to explore this trade-off and we find that while performance is maximized with few large chiplets, and while cost and environmental footprint is minimized with many small chiplets, the optimum balance is achieved with a moderate number of medium-sized chiplets. The optimum number of chiplets depends on the workload and increases with increased inter-chiplet bandwidth.en_US
dc.language.isoengen_US
dc.publisherIEEEen_US
dc.rightsNavngivelse 4.0 Internasjonal*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/deed.no*
dc.titleBalancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUsen_US
dc.title.alternativeBalancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUsen_US
dc.typePeer revieweden_US
dc.typeJournal articleen_US
dc.description.versionacceptedVersionen_US
dc.source.journalIEEE computer architecture lettersen_US
dc.identifier.doi10.1109/LCA.2023.3313203
dc.identifier.cristin2195404
dc.description.localcode© Copyright 2023 IEEE - All rights reserved.en_US
cristin.ispublishedtrue
cristin.fulltextpostprint
cristin.qualitycode1


Tilhørende fil(er)

Thumbnail

Denne innførselen finnes i følgende samling(er)

Vis enkel innførsel

Navngivelse 4.0 Internasjonal
Med mindre annet er angitt, så er denne innførselen lisensiert som Navngivelse 4.0 Internasjonal