Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping

Abstract

This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operations to reach the more beneficial state for storage. A 1-kb SRAM block of low-voltage memory cells was implemented and manufactured in a 130-nm CMOS. The memory cells were made writable and read-stable at low supply voltages with a single-ended write and single-ended read structure using six multithreshold transistors that give rise to an asymmetric retention power. At a supply voltage of 350 mV, the content-dependent leakage power in the asymmetric memory cell is 23 times smaller when storing logic “1”s compared with logic “0”s. A derived statistical model suggests that the mean, wordwise, static power savings of the word-flipping scheme become 15.70% for 8-bit words of uniform bit probability. For the implemented SRAM macro, the mean improvement for the retention power is, including flip logic and decoder and driver overheads, found to be 14.69%. In boundary tests, by writing all words full of undesired values, the power saving becomes 80.37%, while writing all words full of desired values causes a power penalty of 6.14%. Measurement results confirm the improvement in retention power with a ten-chip mean improvement of 11.93% for the same data set.