dc.contributor.author | Reissmann, Nico | |
dc.contributor.author | Meyer, Jan Christian | |
dc.contributor.author | Bahmann, Helge | |
dc.contributor.author | Själander, Magnus | |
dc.date.accessioned | 2021-02-25T13:09:33Z | |
dc.date.available | 2021-02-25T13:09:33Z | |
dc.date.created | 2020-08-14T07:56:38Z | |
dc.date.issued | 2020 | |
dc.identifier.issn | 1539-9087 | |
dc.identifier.uri | https://hdl.handle.net/11250/2730439 | |
dc.description.abstract | Intermediate Representations (IRs) are central to optimizing compilers as the way the program is represented may enhance or limit analyses and transformations. Suitable IRs focus on exposing the most relevant information and establish invariants that different compiler passes can rely on. While control-flow centric IRs appear to be a natural fit for imperative programming languages, analyses required by compilers have increasingly shifted to understand data dependencies and work at multiple abstraction layers at the same time. This is partially evidenced in recent developments such as the Multi-Level Intermediate Representation (MLIR) proposed by Google. However, rigorous use of data flow centric IRs in general purpose compilers has not been evaluated for feasibility and usability as previous works provide no practical implementations. | en_US |
dc.language.iso | eng | en_US |
dc.publisher | ACM | en_US |
dc.title | RVSDG: An intermediate representation for optimizing compilers | en_US |
dc.type | Peer reviewed | en_US |
dc.type | Journal article | en_US |
dc.description.version | acceptedVersion | en_US |
dc.source.journal | ACM Transactions on Embedded Computing Systems | en_US |
dc.identifier.doi | 10.1145/3391902 | |
dc.identifier.cristin | 1823258 | |
dc.description.localcode | © ACM, 2020. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. | en_US |
cristin.ispublished | true | |
cristin.fulltext | postprint | |
cristin.qualitycode | 1 | |