dc.contributor.author | Alipour, Mehdi | |
dc.contributor.author | Kumar, Rakesh | |
dc.contributor.author | Kaxiras, Stefanos | |
dc.contributor.author | Black-Schaffer, David | |
dc.date.accessioned | 2021-02-11T07:24:17Z | |
dc.date.available | 2021-02-11T07:24:17Z | |
dc.date.created | 2021-01-01T22:08:35Z | |
dc.date.issued | 2020 | |
dc.identifier.issn | 1530-0897 | |
dc.identifier.uri | https://hdl.handle.net/11250/2727297 | |
dc.description.abstract | Flexible instruction scheduling is essential for performance in out-of-order processors. This is typically achieved by using CAM-based Instruction Queues (IQs) that provide complete flexibility in choosing ready instructions for execution, but at the cost of significant scheduling energy. In this work we seek to reduce the instruction scheduling energy by reducing the depth and width of the IQ. We do so by classifying instructions based on their readiness and criticality, and using this information to bypass the IQ for instructions that will not benefit from its expensive scheduling structures and delay instructions that will not harm performance. Combined, these approaches allow us to offload a significant portion of the instructions from the IQ to much cheaper FIFO-based scheduling structures without hurting performance. As a result we can reduce the IQ depth and width by half, thereby saving energy. Our design, Delay and Bypass (DNB), is the first design to explicitly address both readiness and criticality to reduce scheduling energy. By handling both classes we are able to achieve 95% of the baseline out-of-order performance while only using 33% of the scheduling energy. This represents a significant improvement over previous designs which addressed only criticality or readiness (91%/89% performance at 74%/53% energy). | en_US |
dc.language.iso | eng | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.title | Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors | en_US |
dc.type | Peer reviewed | en_US |
dc.type | Journal article | en_US |
dc.description.version | acceptedVersion | en_US |
dc.source.journal | IEEE Symposium on High-Performance Computer Architecture (HPCA) | en_US |
dc.identifier.doi | 10.1109/HPCA47549.2020.00042 | |
dc.identifier.cristin | 1864275 | |
dc.description.localcode | © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | en_US |
cristin.ispublished | true | |
cristin.fulltext | postprint | |
cristin.qualitycode | 2 | |