dc.contributor.author | Alipour, Mehdi | |
dc.contributor.author | Kumar, Rakesh | |
dc.contributor.author | Kaxiras, Stefanos | |
dc.contributor.author | Black-Schaffer, David | |
dc.date.accessioned | 2020-01-13T10:55:59Z | |
dc.date.available | 2020-01-13T10:55:59Z | |
dc.date.created | 2019-12-27T18:23:51Z | |
dc.date.issued | 2019 | |
dc.identifier.citation | Design, Automation and Test in Europe (DATE). 2019, 716-721. | nb_NO |
dc.identifier.issn | 1530-1591 | |
dc.identifier.uri | http://hdl.handle.net/11250/2635930 | |
dc.description.abstract | The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order. This work makes the observation that a large number of instructions have both operands ready at dispatch, and therefore do not benefit from out-of-order scheduling. We leverage this to place such ready-at-dispatch instructions in separate, simpler, in-order FIFO queues for scheduling. With such additional queues, we can reduce the size and width of the expensive out-of-order instruction queue, without reducing the processor's overall issue width and depth. Our design, FIFOrder, is able to steer more than 60% of instructions to the cheaper FIFO queues, providing a 50% energy savings over a traditional out-of-order instruction queue design, while delivering 8% higher performance. | nb_NO |
dc.description.abstract | FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors | nb_NO |
dc.language.iso | eng | nb_NO |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | nb_NO |
dc.title | FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors | nb_NO |
dc.type | Journal article | nb_NO |
dc.type | Peer reviewed | nb_NO |
dc.description.version | acceptedVersion | nb_NO |
dc.source.pagenumber | 716-721 | nb_NO |
dc.source.journal | Design, Automation and Test in Europe (DATE) | nb_NO |
dc.identifier.doi | 10.23919/DATE.2019.8715034 | |
dc.identifier.cristin | 1764010 | |
dc.description.localcode | © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | nb_NO |
cristin.unitcode | 194,63,10,0 | |
cristin.unitname | Institutt for datateknologi og informatikk | |
cristin.ispublished | true | |
cristin.fulltext | postprint | |
cristin.qualitycode | 1 | |