Low switching frequency modulation scheme for high power three level converters: FPGA based implementation

Abstract

The demand for electrical motors with high power ratings is increasing in different applications, especially in the offshore industry. The power rating of these motors can be raised by increasing the voltage at the motor terminals to a higher value. This method has the drawback of increasing the losses due to harmonic currents although it fulfills the requirement of increasing the power. An equally important reason to look for a more efficient modulation strategy is that it is not efficient to operate the medium voltage converter at the same switching frequency as the conventional low voltage converters because of high switching losses. To tackle these problems, the PWM technique should be implemented in such a way that it produces the lowest possible harmonic content in the load current. A low switching frequency implementation of the proposed PWM strategy is also an important requirement to alleviate the mentioned problems. One of the ways to do this is programming the pulse patterns so that the total harmonic content fulfills the maximum tolerable harmonic content.In this master?s thesis, techniques to produce the optimal pulse patterns for the motors were studied. First, the mathematical relations that govern the relation between optimal patterns and the required output voltage level were dealt with. Second, a brief study of the Digital control technologies for the implementation of the modulation principle was made with focus on Xilinx FPGA. The flexibility of FPGA based system together with its ability to execute instructions at hardware level made it an ideal choice for the implementation of the proposed modulation scheme. After having mastered the overall development environment of Xilinx FPGA through the studies, the project design, both software and hardware, for the problem in hand was done using the tools.Last, the software program that produces the optimal patterns for a certain variation of number of pulses and modulation indices was successfully developed on the FGPA processor. Finally, an investigation was done on the output waveforms produced by the optimal patterns. It was observed that the pattern change happens as desired, and the optimal patterns produce the required sinusoidal waveform with harmonics less than that which would occur in conventional PWM techniques.