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dc.contributor.authorRamm, Peter
dc.contributor.authorKlumpp, Armin
dc.contributor.authorWeber, Josef
dc.contributor.authorLietaer, Nicolas
dc.contributor.authorTaklo, Maaike M. Visser
dc.contributor.authorde Raedt, W.
dc.contributor.authorFritzsch, Thomas
dc.contributor.authorCouderc, Pascal
dc.date.accessioned2017-10-31T12:33:08Z
dc.date.available2017-10-31T12:33:08Z
dc.date.created2017-02-20T08:42:30Z
dc.date.issued2010
dc.identifier.citationProceedings of ESSCIRC. 2010, 9-16.nb_NO
dc.identifier.issn1930-8833
dc.identifier.urihttp://hdl.handle.net/11250/2463188
dc.description.abstractAs predicted by the ITRS roadmap, semiconductor industry development dominated by shrinking transistor gate dimensions alone will not be able to overcome the performance and cost problems of future IC fabrication. Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. Several full 3D process flows have been demonstrated, however there are still no microelectronic products based on 3D TSV technologies in the market — except CMOS image sensors. 3D chip stacking of memory and logic devices without TSVs is already widely introduced in the market. Applying TSV technology for memory on logic will increase the performance of these advanced products and simultaneously shrink the form factor. In addition to the enabling of further improvement of transistor integration densities, 3D integration is a key technology for integration of heterogeneous technologies. Miniaturized MEMS/IC products represent a typical example for such heterogeneous systems demanding for smart system integration rather than extremely high transistor integration densities. The European 3D technology platform that has been established within the EC funded e-CUBES project is focusing on the requirements coming from heterogeneous systems. The selected 3D integration technologies are optimized concerning the availability of devices (packaged dies, bare dies or wafers) and the requirements of performance and form factor. There are specific technology requirements for the integration of MEMS/NEMS devices which differ from 3D integrated ICs (3D-IC). While 3D-ICs typically show a need for high interconnect densities and conductivities, TSV technologies for the integration of MEMS to ICs may result in lower electrical performance but have to fulfill other requirements, e. g. mechanical stability issues. 3D integration of multiple MEMS/IC stacks was successfully demonstrated for the fabrication of miniaturized sensor systems (e-CUBES), as for automotive, health & fitness and aeronautic applications.nb_NO
dc.language.isoengnb_NO
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)nb_NO
dc.title3D Integration technology: Status and application developmentnb_NO
dc.typeJournal articlenb_NO
dc.typePeer reviewednb_NO
dc.source.pagenumber9-16nb_NO
dc.source.journalProceedings of ESSCIRCnb_NO
dc.identifier.doi10.1109/ESSCIRC.2010.5619857
dc.identifier.cristin1452075
dc.description.localcode(c) 2010 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.nb_NO
cristin.unitcode194,64,45,0
cristin.unitnameInstitutt for konstruksjonsteknikk
cristin.ispublishedtrue
cristin.fulltextpostprint
cristin.qualitycode1


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