Design of a Circuit for Making Test for Load Break Switches

Abstract

A synthetic circuit for making test for load break switches was explained and designed in this master thesis following the IEC standard requirements. Also the voltage drop across the triggered vacuum switch and across the test object were taken into consideration in order to get more realistic results. By having proper values for voltage drops it was possible to find several appropriate combinations of minimum values of resistance, inductance, and capacitance that make a satisfactory making operation possible. The ending results were positive and showed that the making operation was made correctly for a load break switch rated for 24 kV with closing velocity from 1 to 5 meters per second and a triggered vacuum switch with time delay of 50 microseconds. The making current was in the range of 50 to 60 kA without any high-frequency crossing-zero points as expected.