Mechanics of Ultra-Thin Multi-Crystalline Silicon Wafers
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Nowadays, solar energy is one of the important green sources, with more than 80% of all commercial solar cells currently made from silicon wafer. The main purpose of using increasingly thinner silicon wafers for the manufacture of solar cells is to reduce production costs without introducing significant changes in the cell technology, while maximizing silicon utilization. The use of thinner silicon wafers means a higher breakage risk in the production line. A high cost must then be paid to convert poly-silicon into wafers; therefore, careful wafer handling is essential to reduce breakage and associated costs. Furthermore, solar silicon wafers are primarily produced through multi-wire sawing. The sawing process induces microcracks on the wafer’s surface, which are responsible for brittle fractures. Hence, it is important to scrutinize the crack geometries most commonly generated in the sawing or handling process of silicon wafers and link the crack to the wafer fracture. Surface cracks are among the most common defects in solar silicon wafer production. Consequently, a wide range of surface crack configuration parameters was investigated in the first attempt, both analytically and numerically. The ratio of crack depth to wafer thickness ranged from 0.025 to 0.8, while the ratio of crack depth to crack length ranged from 0.001 to 0.8. The results showed that the Newman- Raju solution predicts vanishing SIFs for long surface cracks (a/c≤ 0.01). It indicates that finite element analysis is needed to predict the SIF for long surface cracks in ultra-thin silicon wafers. Also, due to the finite out of plane displacements in the wafer, geometrical nonlinearity should be included in the assessments. Based on the proposed surface crack model, the finite element model has been employed to identify the corresponding surface’s crack geometries by fitting the experimental results obtained by means of 4- point bending- and twisting tests. Experiments displayed that the mechanical strength of the wafers tested parallel to the sawing direction is approximately 15MPa smaller than those tested perpendicular to the sawing direction. After a huge statistical study, the surface cracks with a depth in the range from 10 to 20μm, a length of up to 10mm and angles in the range of ß=30º to 60º were identified as the most common surface crack geometries in the wafers we tested. The stresses produced in the handling and transport, are as important as the presence of structural defects such as cracks, with the types of loading resulting in a different mechanical strength for the sample amplitude (e.g. static loading is usually less critical than vibration). One of the important loading types that has not been focused on in the literature is the vibration of wafers during handling. To carry out the vibration analysis, it is important to understand the factors that influence the natural frequency of thin silicon wafers in the first step. In this study, we applied a nonlinear finite element method to investigate the correlation of the natural frequency of thin solar silicon wafers with material microstructures (grain size and grain orientation), thickness variation and crack geometry (position and size). It has been found that the natural frequency for an anisotropic single crystal silicon wafer is a strong function of material orientation, as less than 10% of a thickness variation will have a negligible effect on natural frequency. It has also been found that cracks smaller than 20mm have no dominant effect on the first five natural frequency modes anywhere in the silicon wafer. The main goal of this part of the study was to show that the multi-crystalline silicon wafer can be modeled as isotropic material in a vibration analysis. After a natural frequency analysis, the second part of the study highlights the key parameters to consider for vibration loading. In particular, it has been found that the rate of loading causing the vibration during handling is very important. Findings within the industry show that the highest amount of breakage in wafers occurs in a suction process which is common to loading during the silicon wafer handling process. Therefore, a systematic approach is employed for the static and dynamic analysis of the suction process. An optimum pad diameter and location is obtained by minimizing the stress distribution in studied cases according to both static and dynamic loading, while the effect of the load rate on the fracture strength is also investigated in this optimum situation. Lastly, to reduce breakage in the suction process, we proposed ultrasound energy as a lubricant between wafers and support. In this regard, an approximate 20 times reduction in handling force was observed in our experiments.